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FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
14 years 29 days ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose
CAV
2004
Springer
108views Hardware» more  CAV 2004»
13 years 11 months ago
Functional Dependency for Verification Reduction
Abstract. The existence of functional dependency among the state variables of a state transition system was identified as a common cause of inefficient BDD representation in formal...
Jie-Hong Roland Jiang, Robert K. Brayton
TVLSI
2002
130views more  TVLSI 2002»
13 years 7 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 22 days ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
ISQED
2006
IEEE
136views Hardware» more  ISQED 2006»
14 years 1 months ago
An Improved AMG-based Method for Fast Power Grid Analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which need to be modeled accurately in circuit design and verification. Meanwhi...
Cheng Zhuo, Jiang Hu, Kangsheng Chen