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ITC
1995
IEEE
116views Hardware» more  ITC 1995»
15 years 7 months ago
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25k gate CMOS Test Chip has been designed, manufac...
Piero Franco, William D. Farwell, Robert L. Stokes...
SDL
2001
89views Hardware» more  SDL 2001»
15 years 5 months ago
Some Implications of MSC, SDL and TTCN Time Extensions for Computer-Aided Test Generation
The purpose of this paper is to describe how computer-aided test generation methods can benefit from the time features and extensions to MSC, SDL and TTCN which are either already ...
Dieter Hogrefe, Beat Koch, Helmut Neukirchen
124
Voted
ENTCS
2002
152views more  ENTCS 2002»
15 years 3 months ago
Contract-based mutation testing in the refinement calculus
This article discusses mutation testing strategies in the context of refinement. Here, a novel generalization of mutation testing techniques is presented to be applied to contract...
Bernhard K. Aichernig
DSD
2010
IEEE
131views Hardware» more  DSD 2010»
15 years 1 months ago
A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder
This paper describes an OMAP-based real-time test bench to find the Pareto frontier of an H.264/SVC decoder within a distortion-energy optimization space. A metric to estimate vide...
F. Pescador, E. Juarez, D. Samper, C. Sanz, Micka&...
231
Voted
CP
2009
Springer
16 years 4 months ago
Constraint-Based Optimal Testing Using DNNF Graphs
The goal of testing is to distinguish between a number of hypotheses about a systemfor example, dierent diagnoses of faults by applying input patterns and verifying or falsifying t...
Anika Schumann, Martin Sachenbacher, Jinbo Huang