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DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 10 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
176
Voted
BMCBI
2008
173views more  BMCBI 2008»
15 years 6 months ago
Improved machine learning method for analysis of gas phase chemistry of peptides
Background: Accurate peptide identification is important to high-throughput proteomics analyses that use mass spectrometry. Search programs compare fragmentation spectra (MS/MS) o...
Allison Gehrke, Shaojun Sun, Lukasz A. Kurgan, Nat...
193
Voted
JTRES
2010
ACM
15 years 6 months ago
WCET driven design space exploration of an object cache
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
Benedikt Huber, Wolfgang Puffitsch, Martin Schoebe...
TII
2011
206views Education» more  TII 2011»
15 years 1 months ago
Timing-Failure Risk Assessment of UML Design Using Time Petri Net Bound Techniques
Abstract—Software systems that do not meet their timing constraints can cause risks. In this work, we propose a comprehensive method for assessing the risk of timing failure by e...
Simona Bernardi, Javier Campos, José Merseg...
SMI
2008
IEEE
101views Image Analysis» more  SMI 2008»
16 years 16 days ago
Fairing wireframes in industrial surface design
Wireframe is a modeling tool widely used in industrial geometric design. The term wireframe refers to two sets of curves, with the property that each curve from one set intersects...
Yu-Kun Lai, Yong-Jin Liu, Yu Zang, Shi-Min Hu