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» Pseudo-Exhaustive Testing of Sequential Circuits
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VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 8 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
DAC
1990
ACM
13 years 12 months ago
Symbolic Simulation - Techniques and Applications
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulat...
Randal E. Bryant
PDP
2003
IEEE
14 years 1 months ago
A Parallel Evolutionary Algorithm for Circuit Partitioning
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
Raul Baños, Consolación Gil, Maria D...
ICCAD
2002
IEEE
107views Hardware» more  ICCAD 2002»
14 years 4 months ago
Characteristic faults and spectral information for logic BIST
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspeciļ¬c spectral information in th...
Xiaoding Chen, Michael S. Hsiao
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
14 years 5 days ago
An approach for improving the levels of compaction achieved by vector omission
We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are ...
Irith Pomeranz, Sudhakar M. Reddy