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ICCAD
2001
IEEE
84views Hardware» more  ICCAD 2001»
14 years 6 months ago
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I...
ISPASS
2010
IEEE
14 years 4 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
IPSN
2010
Springer
14 years 4 months ago
Bayesian optimization for sensor set selection
We consider the problem of selecting an optimal set of sensors, as determined, for example, by the predictive accuracy of the resulting sensor network. Given an underlying metric ...
Roman Garnett, Michael A. Osborne, Stephen J. Robe...
ECBS
2009
IEEE
164views Hardware» more  ECBS 2009»
14 years 4 months ago
Semantically Enhanced Containers for Concurrent Real-Time Systems
Future space missions, such as Mars Science Laboratory, are built upon computing platforms providing a high degree of autonomy and diverse functionality. The increased sophisticat...
Damian Dechev, Peter Pirkelbauer, Nicolas Rouquett...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 4 months ago
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
Adam Flynn, Ann Gordon-Ross, Alan D. George