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» Quadratic placement using an improved timing model
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ISPD
2007
ACM
128views Hardware» more  ISPD 2007»
13 years 8 months ago
X-architecture placement based on effective wire models
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
CVPR
2012
IEEE
11 years 9 months ago
Real time robust L1 tracker using accelerated proximal gradient approach
Recently sparse representation has been applied to visual tracker by modeling the target appearance using a sparse approximation over a template set, which leads to the so-called ...
Chenglong Bao, Yi Wu, Haibin Ling, Hui Ji
GPC
2007
Springer
14 years 26 days ago
Optimizing Server Placement for QoS Requirements in Hierarchical Grid Environments
This paper focuses on two problems related to QoS-aware I/O server placement in hierarchical Grid environments. Given a hierarchical network with requests from clients, the network...
Chien-Min Wang, Chun-Chen Hsu, Pangfeng Liu, Hsi-M...
ISPD
2006
ACM
102views Hardware» more  ISPD 2006»
14 years 20 days ago
A faster implementation of APlace
APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and densi...
Andrew B. Kahng, Qinke Wang
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
13 years 11 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee