Sciweavers

2057 search results - page 19 / 412
» Quadratic placement using an improved timing model
Sort
View
ISPD
2006
ACM
175views Hardware» more  ISPD 2006»
14 years 21 days ago
mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...
IPPS
2006
IEEE
14 years 23 days ago
Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search
In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks,...
Manuel Rubio del Solar, Juan Manuel Sánchez...
GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
13 years 11 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
ISMAR
2009
IEEE
14 years 1 months ago
Online environment model estimation for augmented reality
Augmented reality applications often rely on a detailed environment model to support features such as annotation and occlusion. Usually, such a model is constructed offline, whic...
Jonathan Ventura, Tobias Höllerer
DATE
2007
IEEE
117views Hardware» more  DATE 2007»
14 years 1 months ago
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in in...
Shweta Srivastava, Jaijeet S. Roychowdhury