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LCTRTS
2001
Springer
14 years 2 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
DATE
2002
IEEE
108views Hardware» more  DATE 2002»
14 years 3 months ago
Networks on Silicon: Combining Best-Effort and Guaranteed Services
We advocate a network on silicon (NOS) as a hardware architecture to implement communication between IP cores in future technologies, and as a software model in the form of a prot...
Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeter...
HPCA
2002
IEEE
14 years 10 months ago
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
Power dissipation has become one of the most critical factors for the continued development of both high-end and low-end computer systems. The successful design and evaluation of ...
Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary J...
EFDBS
2003
13 years 11 months ago
Four-Level-Architecture for Closure in Interoperability
A definition of types in an information system is given from ld abstractions through data constructs, schema and definitions to physical data values. Category theory suggests tha...
B. Nick Rossiter, Michael A. Heather
DAC
2003
ACM
14 years 11 months ago
Automated synthesis of efficient binary decoders for retargetable software toolkits
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
Wei Qin, Sharad Malik