Sciweavers

352 search results - page 22 / 71
» Quantifying Instruction Criticality
Sort
View
IPPS
2006
IEEE
14 years 5 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
TC
2002
13 years 10 months ago
On Augmenting Trace Cache for High-Bandwidth Value Prediction
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
Sang Jeong Lee, Pen-Chung Yew
APCSAC
2003
IEEE
14 years 2 months ago
Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran
IM
2003
14 years 9 days ago
A Revenue-based Model for Making Resource Investment Decisions in IP Networks
: Capacity planning is a critical task in network management. It identifies how much capacity is needed to match future traffic demand. It directly affects customer satisfaction ...
Srinivasan Jagannathan, Jörn Altmann, Lee Rho...
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 7 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...