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DATE
2008
IEEE
171views Hardware» more  DATE 2008»
14 years 5 months ago
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
CC
2003
Springer
192views System Software» more  CC 2003»
14 years 4 months ago
Address Register Assignment for Reducing Code Size
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...
Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, ...
CC
2008
Springer
240views System Software» more  CC 2008»
14 years 22 days ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
JCP
2008
216views more  JCP 2008»
13 years 11 months ago
Design Overview Of Processor Based Implantable Pacemaker
Implantable pacemaker is a battery operated real time embedded system, which includes software/hardware codesign strategy. As it is placed within the heart by surgery, battery life...
Santosh D. Chede, Kishore D. Kulat
WSC
2000
14 years 8 days ago
Predicting enemy force closure with simulation
This paper presents a model and an analysis done to predict enemy force closure. The simulation replaces a pencil and ruler method that has been used by Department of Defense plan...
Mark R. Grabau, Michael D. Payne