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» Quantifying Instruction Criticality
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MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
14 years 3 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
JILP
2000
109views more  JILP 2000»
13 years 10 months ago
Dynamic Register Renaming Through Virtual-Physical Registers
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instructio...
Teresa Monreal, Antonio González, Mateo Val...
JDS
2007
104views more  JDS 2007»
13 years 10 months ago
Operational Risk Management How an I-DSS May Help
Operational Risk management, the least covered component of Enterprise Wide Risk Management, needs intelligent tools to implement Comprehensive Emergency Management Programs. In t...
Pedro A. C. Sousa, João Paulo Pimentã...
DATE
2003
IEEE
65views Hardware» more  DATE 2003»
14 years 4 months ago
Masking the Energy Behavior of DES Encryption
Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has d...
Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T....
PPOPP
2009
ACM
14 years 11 months ago
Idempotent work stealing
Load balancing is a technique which allows efficient parallelization of irregular workloads, and a key component of many applications and parallelizing runtimes. Work-stealing is ...
Maged M. Michael, Martin T. Vechev, Vijay A. Saras...