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» Quantifying Instruction Criticality
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EUROSYS
2010
ACM
14 years 3 months ago
Locating cache performance bottlenecks using data profiling
Effective use of CPU data caches is critical to good performance, but poor cache use patterns are often hard to spot using existing execution profiling tools. Typical profilers at...
Aleksey Pesterev, Nickolai Zeldovich, Robert T. Mo...
ACSC
2004
IEEE
14 years 2 months ago
Reducing Register Pressure Through LAER Algorithm
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
Gao Song
ETS
2000
IEEE
141views Hardware» more  ETS 2000»
13 years 10 months ago
Web-Supported Emergent-Collaboration In Higher Education Courses
This study focused on the integration of a Web shell for supporting emergent-collaboration activities in six graduate courses (115 students) in the Tel-Aviv University School of E...
Rafi Nachmias, David Mioduser, Avigail Oren, Judit...
ET
2008
92views more  ET 2008»
13 years 10 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ISPASS
2006
IEEE
14 years 5 months ago
Comparing simulation techniques for microarchitecture-aware floorplanning
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...