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CODES
2005
IEEE
14 years 4 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung
IEEEINTERACT
2003
IEEE
14 years 4 months ago
Compiler-Directed Resource Management for Active Code Regions
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel ...
MICRO
2000
IEEE
61views Hardware» more  MICRO 2000»
14 years 3 months ago
Reducing wire delay penalty through value prediction
In this work we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating...
Joan-Manuel Parcerisa, Antonio González
SIGMETRICS
2000
ACM
14 years 3 months ago
An analytical model of the working-set sizes in decision-support systems
This paper presents an analytical model to study how working sets scale with database size and other applications parameters in decision-support systems (DSS). The model uses appl...
Magnus Karlsson, Per Stenström
ISSS
1997
IEEE
103views Hardware» more  ISSS 1997»
14 years 3 months ago
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
Chih-Tung Chen, Kayhan Küçük&cced...