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IPPS
2009
IEEE
14 years 3 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...
ISPASS
2008
IEEE
14 years 2 months ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey
CC
2007
Springer
109views System Software» more  CC 2007»
14 years 2 months ago
Layout Transformations for Heap Objects Using Static Access Patterns
As the amount of data used by programs increases due to the growth of hardware storage capacity and computing power, efficient memory usage becomes a key factor for performance. Si...
Jinseong Jeon, Keoncheol Shin, Hwansoo Han
CONCURRENCY
2007
95views more  CONCURRENCY 2007»
13 years 8 months ago
Automated and accurate cache behavior analysis for codes with irregular access patterns
Abstract. The memory hierarchy plays an essential role in the performance of current computers, thus good analysis tools that help predict and understand its behavior are required....
Diego Andrade, Manuel Arenaz, Basilio B. Fraguela,...
ICCAD
2003
IEEE
136views Hardware» more  ICCAD 2003»
14 years 5 months ago
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...