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» Quasi-Resonant Interconnects: A Low Power Design Methodology
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ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
14 years 4 months ago
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharide...
DAC
2000
ACM
14 years 9 months ago
GTX: the MARCO GSRC technology extrapolation system
Technology extrapolation -- the calibration and prediction of achievable design in future technology generations ? drives the evolution of VLSI system architectures, design method...
Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farin...
DAC
1999
ACM
14 years 9 months ago
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
SIGMETRICS
2003
ACM
129views Hardware» more  SIGMETRICS 2003»
14 years 1 months ago
Run-time modeling and estimation of operating system power consumption
The increasing constraints on power consumption in many computing systems point to the need for power modeling and estimation for all components of a system. The Operating System ...
Tao Li, Lizy Kurian John
DAC
2006
ACM
14 years 9 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu