79 search results - page 3 / 16 » Queues, stores, and tableaux |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
COMPUTING
2008
13 years 7 months ago
2008
We introduce two data-structural transformations to construct doubleended priority queues from priority queues. To apply our transformations the priority queues exploited must sup...
WADS
2007
Springer
14 years 1 months ago
2007
Springer
In the faulty-memory RAM model, the content of memory cells can get corrupted at any time during the execution of an algorithm, and a constant number of uncorruptible registers are...