211 search results - page 12 / 43 » REDEFIS: a system with a redefinable instruction set process... |
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
HIPEAC
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
RECOSOC
2007
13 years 9 months ago
2007
Code Compression has been shown to be efficient in minimizing the memory requirements for embedded systems as well as in power consumption reduction and performance improvement. I...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Application-specific customization of the instruction set helps embedded processors achieve significant performance and power efficiency. In this paper, we explore customizatio...