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» RISPP: Rotating Instruction Set Processing Platform
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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 1 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
14 years 2 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
SOSP
1997
ACM
13 years 9 months ago
Towards Transparent and Efficient Software Distributed Shared Memory
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...
Daniel J. Scales, Kourosh Gharachorloo
IEEEPACT
2000
IEEE
14 years 4 days ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
SRDS
2007
IEEE
14 years 2 months ago
RandSys: Thwarting Code Injection Attacks with System Service Interface Randomization
Code injection attacks are a top threat to today’s Internet. With zero-day attacks on the rise, randomization techniques have been introduced to diversify software and operation...
Xuxian Jiang, Helen J. Wang, Dongyan Xu, Yi-Min Wa...