Sciweavers

375 search results - page 41 / 75
» RTL power estimation and optimization
Sort
View
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
14 years 2 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
DAC
2010
ACM
13 years 7 months ago
Adaptive and autonomous thermal tracking for high performance computing systems
Many DTM schemes rely heavily on the accurate knowledge of the chip's dynamic thermal state to make optimal performance/ temperature trade-off decisions. This information is ...
Yufu Zhang, Ankur Srivastava
ICASSP
2010
IEEE
13 years 7 months ago
Designing the Wiener post-filter for diffuse noise suppression using imaginary parts of inter-channel cross-spectra
This paper describes a new design of the Wiener post-filter for diffuse noise suppression. The Wiener post-filter is well-known as an effective post-processing of the minimum va...
Nobutaka Ito, Nobutaka Ono, Emmanuel Vincent, Shig...
WWW
2006
ACM
14 years 8 months ago
Wake-on-WLAN
In bridging the digital divide, two important criteria are cost-effectiveness, and power optimization. While 802.11 is cost-effective and is being used in several installations in...
Nilesh Mishra, Kameswari Chebrolu, Bhaskaran Raman...