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» RTOS Modeling for System Level Design
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FDL
2006
IEEE
15 years 10 months ago
Formalizing TLM with Communicating State Machines
Transaction Level Models are widely being used as high-level reference models during embedded systems development. High simulation speed and great modeling flexibility are the ma...
Bernhard Niemann, Christian Haubelt
ICSE
2003
IEEE-ACM
16 years 4 months ago
Architectural Level Risk Assessment Tool Based on UML Specifications
Recent evidences indicate that most faults in software systems are found in only a few of a system's components [1]. The early identification of these components allows an or...
T. Wang, Ahmed E. Hassan, Ajith Guedem, Walid Abde...
160
Voted
ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
14 years 7 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
135
Voted
DATE
2009
IEEE
151views Hardware» more  DATE 2009»
15 years 10 months ago
Combined system synthesis and communication architecture exploration for MPSoCs
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
Martin Lukasiewycz, Martin Streubühr, Michael...
CIMCA
2006
IEEE
15 years 10 months ago
Assessing and Assuring Trust in E-Commerce Systems
On-line trading or Internet Commerce restoring to ECommerce systems are gradually replacing the traditional commerce activities. Internet users must have reasonable faith on the u...
Zhongwei Zhang, Zhen Wang