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ITC
1997
IEEE
129views Hardware» more  ITC 1997»
14 years 1 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
DAC
2004
ACM
14 years 24 days ago
Probabilistic regression suites for functional verification
Random test generators are often used to create regression suites on-the-fly. Regression suites are commonly generated by choosing several specifications and generating a number o...
Shai Fine, Shmuel Ur, Avi Ziv
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
14 years 24 days ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki
SMA
2010
ACM
171views Solid Modeling» more  SMA 2010»
13 years 9 months ago
Efficient simplex computation for fixture layout design
Designing a fixture layout of an object can be reduced to computing the largest simplex and the resulting simplex is classified using the radius of the largest inscribed ball cent...
Yu Zheng, Ming C. Lin, Dinesh Manocha
TIT
2002
129views more  TIT 2002»
13 years 8 months ago
Arbitrary source models and Bayesian codebooks in rate-distortion theory
-- We characterize the best achievable performance of lossy compression algorithms operating on arbitrary random sources, and with respect to general distortion measures. Direct an...
Ioannis Kontoyiannis, Junshan Zhang