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» Rapid estimation of power consumption for hybrid FPGAs
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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 4 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
DAC
2003
ACM
14 years 18 days ago
Crosstalk noise in FPGAs
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
Yajun Ran, Malgorzata Marek-Sadowska
ISER
2004
Springer
128views Robotics» more  ISER 2004»
14 years 22 days ago
Towards High-Fidelity On-Board Attitude Estimation for Legged Locomotion via a Hybrid Range and Inertial Approach
Legged robots display a characteristically periodic motion. Measuring and tracking this motion has traditionally been performed using general inertial measurement techniques. While...
Surya P. N. Singh, Kenneth J. Waldron
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 4 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
ERSA
2008
185views Hardware» more  ERSA 2008»
13 years 8 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George