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    ISCA
    2003
    IEEE
    120views Hardware» more  ISCA 2003»
    ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes
    14 years 3 days ago
    ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes
    Download  iacoma.cs.uiuc.edu
    While removing software bugs consumes vast amounts of human time, hardware support for debugging in modern computers remains rudimentary. Fortunately, we show that mechanisms for ...
    Milos Prvulovic, Josep Torrellas
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    ISCA
    2006
    IEEE
    142views Hardware» more  ISCA 2006»
    Bulk Disambiguation of Speculative Threads in Multiprocessors
    14 years 25 days ago
    Bulk Disambiguation of Speculative Threads in Multiprocessors
    Download  iacoma.cs.uiuc.edu
    Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
    Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
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