551 search results - page 63 / 111 » Realizability of Real-Time Logics |
124
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
150
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SBCCI
2006
ACM
15 years 12 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
162
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CORR
2010
Springer
15 years 27 days ago
2010
Springer
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
157
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IOLTS
2003
IEEE
15 years 11 months ago
2003
IEEE
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
175
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COLING
2002
15 years 5 months ago
2002
Meaning shifting phenomena such as metonymy have recently attracted increasing interest of researchers. Though these phenomena have been addressed by plenty of computational metho...