As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyu...
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...
Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Ch...
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...