174 search results - page 22 / 35 » Reclocking for high-level synthesis |
CEC
2008
IEEE
14 years 1 months ago
2008
IEEE
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
OOPSLA
2010
Springer
13 years 5 months ago
2010
Springer
Given a high-level specification and a low-level programming language, our goal is to automatically synthesize an efficient program that meets the specification. In this paper,...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
ISLPED
2003
ACM
14 years 22 days ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...