174 search results - page 25 / 35 » Reclocking for high-level synthesis |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
RSP
2006
IEEE
14 years 1 months ago
2006
IEEE
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
VLSI
2005
Springer
14 years 29 days ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
FASE
2003
Springer
14 years 21 days ago
2003
Springer
Scenarios are powerful tools to model and analyze software systems. However, since they do not provide a complete description of the system, but just some possible execution paths,...
DAC
2009
ACM
14 years 4 days ago
2009
ACM
We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...