174 search results - page 9 / 35 » Reclocking for high-level synthesis |
JNIT
2010
13 years 2 months ago
2010
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
EVOW
2001
Springer
14 years 1 days ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symm...