230 search results - page 37 / 46 » Reconfigurable Fast Memory Management System Design for Appl... |
JCC
2008
13 years 8 months ago
2008
: For the new parallel implementation of electronic structure methods in ACES III (Lotrich et al., in preparation) the present state-of-the-art algorithms for the evaluation of ele...
CASES
2010
ACM
13 years 6 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
VLSID
2009
IEEE
14 years 9 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...