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DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 1 months ago
Test compaction for transition faults under transparent-scan
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
Irith Pomeranz, Sudhakar M. Reddy
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
14 years 21 days ago
Test Data Compression Using Dictionaries with Fixed-Length Indices
—We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of...
Lei Li, Krishnendu Chakrabarty
GLVLSI
2002
IEEE
98views VLSI» more  GLVLSI 2002»
14 years 11 days ago
Minimizing concurrent test time in SoC's by balancing resource usage
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 15 days ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
DFT
2005
IEEE
102views VLSI» more  DFT 2005»
13 years 9 months ago
Using Statistical Transformations to Improve Compression for Linear Decompressors
Linear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, an...
Samuel I. Ward, Chris Schattauer, Nur A. Touba