740 search results - page 57 / 148 » Recursive layout generation |
108
Voted
ICCAD
2005
IEEE
15 years 11 months ago
2005
IEEE
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
89
Voted
VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten...
110
click to vote
INFOCOM
2008
IEEE
15 years 8 months ago
2008
IEEE
—We study the problem of localizing a large sensor network having a complex shape, possibly with holes. A major challenge with respect to such networks is to figure out the corr...
115
click to vote
SIGGRAPH
2010
ACM
15 years 6 months ago
2010
ACM
Paper architectures are 3D paper buildings created by folding and cutting. The creation process of paper architecture is often laborintensive and highly skill-demanding, even with...
126
click to vote
DAC
2012
ACM
13 years 4 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...