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CF
2007
ACM
14 years 1 months ago
Automated generation of layout and control for quantum circuits
We present a computer-aided design flow for quantum circuits, complete with automatic layout and control logic extraction. To motivate automated layout for quantum circuits, we in...
Mark Whitney, Nemanja Isailovic, Yatish Patel, Joh...
SIGMOD
2010
ACM
157views Database» more  SIGMOD 2010»
13 years 9 months ago
Workload-aware storage layout for database systems
The performance of a database system depends strongly on the layout of database objects, such as indexes or tables, onto the underlying storage devices. A good layout will both ba...
Oguzhan Ozmen, Kenneth Salem, Jiri Schindler, Stev...
DATE
2008
IEEE
109views Hardware» more  DATE 2008»
14 years 4 months ago
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 4 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
GD
2003
Springer
14 years 2 months ago
The Puzzle Layout Problem
We address the new problem of puzzle layout as a new application of awing. We present two abstract models of puzzles, permutation puzzles and cyclic puzzles, which can be modeled a...
Kozo Sugiyama, Seok-Hee Hong, Atsuhiko Maeda