466 search results - page 64 / 94 » Reduce, reuse |
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must b...
SOSP
2009
ACM
14 years 5 months ago
2009
ACM
Faulty device drivers cause significant damage through down time and data loss. The problem can be mitigated by an improved driver development process that guarantees correctness...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
HPDC
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper presents the concept of pluggable parallelisation that allows scientists to develop “sequential like” codes that can take advantage of multi-core, cluster and grid ...