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SASP
2009
IEEE
222views Hardware» more  SASP 2009»
14 years 2 months ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
ISMVL
2003
IEEE
83views Hardware» more  ISMVL 2003»
14 years 27 days ago
Multiple-Valued Dynamic Source-Coupled Logic
A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evalua...
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyam...
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 1 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
ARITH
1997
IEEE
13 years 12 months ago
On the Design of IEEE Compliant Floating Point Units
Engineering design methodology recommends designing a system as follows: Start with an unambiguous speci cation, partition the system into blocks, specify the functionality of eac...
Guy Even, Wolfgang J. Paul
IEICET
2008
106views more  IEICET 2008»
13 years 7 months ago
Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Comm
Finite impulse response (FIR) filtering is the most computationally intensive operation in the channelizer of a wireless communication receiver. Higher order FIR channel filters a...
Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund ...