31 search results - page 2 / 7 » Reduced Latency IEEE Floating-Point Standard Adder Architect... |
ASAP
2008
IEEE
14 years 3 months ago
2008
IEEE
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
ARVLSI
1995
IEEE
14 years 2 days ago
1995
IEEE
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
VLSID
2006
IEEE
14 years 2 months ago
2006
IEEE
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
FCCM
2003
IEEE
14 years 1 months ago
2003
IEEE
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
ASAP
2007
IEEE
13 years 10 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...