58 search results - page 2 / 12 » Reduced design time by load distribution with CAD framework ... |
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
ISCAS
1999
IEEE
14 years 25 days ago
1999
IEEE
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
SPAA
2005
ACM
14 years 2 months ago
2005
ACM
Switching cells in parallel is a common approach to build switches with very high external line rate and a large number of ports. A prime example is the parallel packet switch (in...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
In recent years, we have seen a dramatic increase in the use of data-centric distributed systems such as global grid infrastructures, sensor networks, network monitoring, and vari...
TVLSI
2002
13 years 8 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...