Sciweavers

663 search results - page 131 / 133
» Reducing Compilation Time Overhead in Compiled Simulators
Sort
View
DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
ICPP
2009
IEEE
14 years 2 months ago
On Maximum Stability with Enhanced Scalability in High-Churn DHT Deployment
Abstract—When applied in a commercial deployment, DHTbased P2P protocols face a dilemma: although most real-world participants are so unstable that the maintenance overhead is pr...
Junfeng Xie, Zhenhua Li, Guihai Chen, Jie Wu
SAMOS
2009
Springer
14 years 2 months ago
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks
Developing real time multimedia applications for best effort networks such as the Internet requires prohibitions against jitter delay and frame loss. This problem is further compl...
Roya Choupani, Stephan Wong, Mehmet R. Tolun
BROADNETS
2005
IEEE
14 years 1 months ago
A Lightweight framework for source-to-sink data transfer in wireless sensor networks
— Lightweight protocols that are both bandwidth and power thrifty are desirable for sensor networks. In addition, for many sensor network applications, timeliness of data deliver...
James Jobin, Zhenqiang Ye, Honomount Rawat, Srikan...
CODES
2005
IEEE
14 years 1 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...