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» Reducing Compilation Time Overhead in Compiled Simulators
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DSD
2010
IEEE
153views Hardware» more  DSD 2010»
13 years 8 months ago
Simulation of High-Performance Memory Allocators
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
José Luis Risco-Martín, José ...
CASES
2003
ACM
14 years 1 months ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
CGO
2004
IEEE
13 years 11 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
CC
2010
Springer
155views System Software» more  CC 2010»
14 years 2 months ago
Preference-Guided Register Assignment
Abstract. This paper deals with coalescing in SSA-based register allocation. Current coalescing techniques all require the interference graph to be built. This is generally conside...
Matthias Braun, Christoph Mallon, Sebastian Hack
KR
2004
Springer
14 years 1 months ago
Planning Graphs and Knowledge Compilation
One of the major advances in classical planning has been the development of Graphplan. Graphplan builds a layered structure called the planning graph, and then searches this struc...
Hector Geffner