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» Reducing Compilation Time Overhead in Compiled Simulators
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DAC
1994
ACM
14 years 4 days ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain
LCTRTS
2007
Springer
14 years 2 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
IPPS
1999
IEEE
14 years 10 days ago
Optimizing Irregular HPF Applications using Halos
This paper presents language features for High Performance Fortran HPF to specify non-local access patterns of distributed arrays, called halos, and to control the communication as...
Siegfried Benkner
SIGMETRICS
1994
ACM
113views Hardware» more  SIGMETRICS 1994»
14 years 3 days ago
Shade: A Fast Instruction-Set Simulator for Execution Profiling
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...
Robert F. Cmelik, David Keppel
AICCSA
2007
IEEE
99views Hardware» more  AICCSA 2007»
14 years 1 days ago
An Efficient Processor Allocation Strategy that Maintains a High Degree of Contiguity among Processors in 2D Mesh Connected Mult
Two strategies are used for the allocation of jobs to processors connected by mesh topologies: contiguous allocation and non-contiguous allocation. In noncontiguous allocation, a ...
Saad Bani-Mohammad, Mohamed Ould-Khaoua, Ismail Ab...