60 search results - page 3 / 12 » Reducing DRAM Latencies with an Integrated Memory Hierarchy ... |
CODES
2011
IEEE
12 years 6 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
MICRO
2006
IEEE
14 years 18 days ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
ISPASS
2007
IEEE
14 years 26 days ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...