155 search results - page 2 / 31 » Reducing Design Complexity of the Load Store Queue |
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
PATMOS
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
ISLPED
2006
ACM
14 years 2 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...