155 search results - page 3 / 31 » Reducing Design Complexity of the Load Store Queue |
IBMRD
2006
13 years 8 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
ICPP
1999
IEEE
14 years 9 days ago
1999
IEEE
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
PACS
2000
Springer
13 years 11 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...