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ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 21 days ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
HPCA
2007
IEEE
14 years 1 months ago
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
Albert Meixner, Daniel J. Sorin
ARCS
2010
Springer
13 years 11 months ago
A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems
Power and resource management are key goals for the success of modern battery-supplied multimedia devices. This kind of devices are usually based on SoCs with a wide range of subsy...
Patrick Bellasi, William Fornaciari, David Siorpae...
CODES
2011
IEEE
12 years 7 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
HPCA
1996
IEEE
13 years 11 months ago
A Comparison of Entry Consistency and Lazy Release Consistency Implementations
This paper compares several implementations of entry consistency (EC) and lazy release consistency (LRC), two relaxed memory models in use with software distributed shared memory ...
Sarita V. Adve, Alan L. Cox, Sandhya Dwarkadas, Ra...