Sciweavers

3702 search results - page 662 / 741
» Reducing Misclassification Costs
Sort
View
ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
14 years 3 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
14 years 3 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras
LCN
2008
IEEE
14 years 3 months ago
Firewalling wireless sensor networks: Security by wireless
—Networked sensors and actuators for purposes from production monitoring and control to home automation are in increasing demand. Until recently, the main focus laid on wired sys...
Ivan Martinovic, Nicos Gollan, Jens B. Schmitt
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
14 years 3 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
NOCS
2008
IEEE
14 years 3 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...