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» Reducing Parallel Overheads Through Dynamic Serialization
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DATE
2007
IEEE
98views Hardware» more  DATE 2007»
14 years 3 months ago
A one-shot configurable-cache tuner for improved energy and performance
We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application....
Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A...
CCGRID
2005
IEEE
14 years 2 months ago
A novel workload migration scheme for heterogeneous distributed computing
Dynamically partitioning of adaptive applications and migration of excess workload from overloaded processors to underloaded processors during execution are critical techniques ne...
Yawei Li, Zhiling Lan
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 1 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
VEE
2009
ACM
130views Virtualization» more  VEE 2009»
14 years 1 months ago
Post-copy based live virtual machine migration using adaptive pre-paging and dynamic self-ballooning
We present the design, implementation, and evaluation of post-copy based live migration for virtual machines (VMs) across a Gigabit LAN. Live migration is an indispensable feature...
Michael R. Hines, Kartik Gopalan
DAGSTUHL
2006
13 years 10 months ago
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
Douglas L. Maskell, Timothy F. Oliver