293 search results - page 12 / 59 » Reducing Power with Performance Constraints for Parallel Spa... |
SAMOS
2010
Springer
13 years 5 months ago
2010
Springer
A new heterogeneous multiprocessor system with dynamic memory and power management for improved performance and power consumption is presented. Increased data locality is automatic...
HPCC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. We improve the performance of sparse matrix-vector multiplication (SpMV) on modern cache-based superscalar machines when the matrix structure consists of multiple, irregu...
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
ISLPED
2000
ACM
13 years 12 months ago
2000
ACM
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
ICCCN
2007
IEEE
14 years 1 months ago
2007
IEEE
In the past decade cluster computing platforms have been widely applied to support a variety of scientific and commercial applications, many of which are parallel in nature. Howev...