293 search results - page 14 / 59 » Reducing Power with Performance Constraints for Parallel Spa... |
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model...
HOTI
2011
IEEE
12 years 7 months ago
2011
IEEE
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
CP
2005
Springer
14 years 1 months ago
2005
Springer
Abstract Competition and cooperation can boost the performance of a combinatorial search process. Both can be implemented with a portfolio of algorithms which run in parallel, give...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
CLUSTER
2007
IEEE
13 years 11 months ago
2007
IEEE
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...