293 search results - page 17 / 59 » Reducing Power with Performance Constraints for Parallel Spa... |
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperat...
ICIP
1995
IEEE
14 years 9 months ago
1995
IEEE
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the stateof-the-ar...
TWC
2008
13 years 7 months ago
2008
In this paper, we investigate the application of nonbinary low-density parity-check (LDPC) cycle codes over Galois field GF(q) to multiple-input multiple-output (MIMO) channels. Tw...