293 search results - page 54 / 59 » Reducing Power with Performance Constraints for Parallel Spa... |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
PODC
2009
ACM
14 years 8 months ago
2009
ACM
Consider a setting where nodes can vary their transmission power thereby changing the network topology, the goal of topology control is to reduce the transmission power while ensu...
ADHOCNOW
2009
Springer
14 years 2 months ago
2009
Springer
Abstract— Mobile wireless sensor networks have to be robust against the limitations of the underlying platform. While lightweight form factor makes them an attractive choice for ...
ISCA
2011
IEEE
2011
IEEE
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
12 years 11 months ago
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...