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DAC
2010
ACM
13 years 11 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
LICS
2003
IEEE
14 years 25 days ago
Revisiting Digitization, Robustness, and Decidability for Timed Automata
We consider several questions related to the use of digitization techniques for timed automata. These very successful techniques reduce dense-time language inclusion problems to d...
Joël Ouaknine, James Worrell
CODES
2007
IEEE
14 years 1 months ago
Ensuring secure program execution in multiprocessor embedded systems: a case study
Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered sec...
Krutartha Patel, Sridevan Parameswaran, Seng Lin S...
SDM
2008
SIAM
134views Data Mining» more  SDM 2008»
13 years 9 months ago
Direct Density Ratio Estimation for Large-scale Covariate Shift Adaptation
Covariate shift is a situation in supervised learning where training and test inputs follow different distributions even though the functional relation remains unchanged. A common...
Yuta Tsuboi, Hisashi Kashima, Shohei Hido, Steffen...
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
13 years 11 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...